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?1 CXD2452R e96830c9x timing generator for progressive scan ccd image sensor description the CXD2452R is a timing generator which generates the timing pulses for performing progressive scan readout for digital still cameras and personal computer image input applications using the icx098ak ccd image sensor. features base oscillation frequency 36.81mhz (2340f h ) monitoring readout allowed high-speed/low-speed electronic shutter function horizontal driver for ccd image sensor signal processor ic system clock generation 1170f h , 780f h vertical/horizontal sync (ssg) timing generation applications digital still cameras personal computer image input structure silicon gate cmos ic pin configuration absolute maximum ratings supply voltage v dd vss ?0.5 to +7.0 v input voltage v i vss ?0.5 to v dd + 0.5 v output voltage v o vss ?0.5 to v dd + 0.5 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage v dd a, v dd b, v dd c, v dd d 3.0 to 3.6 v operating temperature topr ?0 to +75 ? applicable ccd image sensors icx098ak (type 1/4 ccd) sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 48 pin lqfp (plastic) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 1 osci 3mck v ss 1 wen test v dd 1 xclpob h1 v ss 2 rg v dd 2 v ss 5 cld fri hri hro fro ebcksm sen ssk ssi v dd 6 rst osco xv1 v dd 7 xsub xv2 xsg2 xv3 v ss 6 mck dsgat h2 v dd 3 v dd 4 xshp xshd v ss 4 1/2mck id v ss 3 xclpdm xrs v dd 5 pblk xsg1 3/2mck *groups of pins enclosed in the fingure indicate sections for which power supply separationis possible.
? 2 CXD2452R block diagram 3 4 7 1 5 2 1 3 0 4 0 3 7 3 4 3 1 3 3 w e n t e s t x c l p d m x c l p o b 1 2 h 1 9 r g r s t f r i h r i h r o f r o e b c k s m s e n s s k s s i x s u b d s g a t 1 3 h 2 i d 1 7 1 8 1 9 x s h p x s h d x r s p b l k 4 1 4 2 4 3 4 4 4 6 x v 1 x v 2 x s g 2 x v 3 x s g 1 l a t c h 2 7 2 8 2 9 l a t c h l a t c h h r i d i f f e r e n t i a l 1 / 2 1 / 3 1 / 2 1 / 3 9 0 1 / 5 2 5 s s g 3 2 5 r e g i s t e r p u l s e g e n e r a t o r 2 8 1 0 1 1 1 4 1 6 2 0 2 4 2 6 3 9 3 8 3 5 4 5 4 7 4 8 1 o s c i 3 m c k v s s c l d v d d 1 / 2 m c k o s c o m c k 3 6 6 2 5 3 / 2 m c k 2 3 1 / 2 2 2
? 3 CXD2452R pin description pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 3mck vss1 wen id test v dd 1 xclpob v dd 2 rg vss2 vss3 h1 h2 v dd 3 xclpdm v dd 4 xshp xshd xrs vss4 pblk 1/2mck 3/2mck v dd 5 rst v dd 6 ssi ssk sen ebcksm fro i o o i o o o o o o o o o o i i i i i o internal main clock. (2340f h ) gnd memory write timing. stop control possible using the serial interface data. vertical direction line identification pulse output. stop control possible using the serial interface data. ic test pin; normally fixed to gnd. (with pull-down resistor) 3.3v power supply. (power supply for common logic block) ccd optical black signal clamp pulse output. stop control possible using the serial interface data. 3.3v power supply. (power supply for rg) ccd reset gate pulse output. (780f h ) gnd gnd ccd horizontal register drive clock output. (780f h ) ccd horizontal register drive clock output. (780f h ) 3.3v power supply. (power supply for h1/h2) pulse output for dummy bit block clamp . 3.3v power supply. (power supply for cds system) precharge level sample-and-hold pulse output. (780f h ) data level sample-and-hold pulse output. (780f h ) sample-and-hold pulse output for analog/digital conversion phase alignment. (780f h ) gnd pulse output for horizontal and vertical blanking interval pulse cleaning. horizontal direction pixel identification pulse output. stop control possible using the serial interface data. system clock output for signal processing ic (1170f h ). stop control possible using the serial interface data. 3.3v power supply. (power supply for common logic block) internal system reset input. high: normal status, low: reset status always input one reset pulse after power-on. 3.3v power supply. (power supply for common logic block) serial interface data input for internal mode settings. serial interface clock input for internal mode settings. serial interface strobe input for internal mode settings. chksum enable. (with pull-down resistor) high: sum check invalid, low: sum check valid vertical sync signal output. stop control possible using the serial interface data. symbol i/o description
? 4 CXD2452R 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 hro hri fri cld v ss 5 dsgat mck vss6 xsub xv3 xsg2 xsg1 xv2 v dd 7 xv1 osco osci o i i o i o o o o o o o o i horizontal sync signal output. stop control possible using the serial interface data. horizontal sync signal input. vertical sync signal input. clock output for analog/digital conversion ic. (780f h ) phase adjustment in 60 units possible using the serial interface data. gnd control input used to stop pulse generation for ccd image sensor, sample-and- hold ic and analog/digital conversion ic. high: normal status, low: stop status controlled pulse can be changed using the serial interface data. system clock output for signal processor ic. (780f h ) gnd pulse output for electronic shutter. ccd vertical register drive pulse output. ccd sensor readout pulse output. ccd sensor readout pulse output. ccd vertical register drive pulse output. 3.3v power supply. (power supply for common logic block) ccd vertical register drive pulse output. inverter output for oscillation. inverter input for oscillation. pin no. symbol i/o description
? 5 CXD2452R electrical characteristics dc characteristics (within the recommended operating conditions) item pins symbol conditions min. typ. max. unit * 1 these input pins do not have protective diodes on the internal power supply side. * 2 these input pins have internal pull-down resistors. * 3 the above table indicates the condition for 3.3v drive. supply voltage 1 supply voltage 2 supply voltage 3 supply voltage 4 input voltage 1 * 1 input voltage 2 * 1 * 2 input voltage 3 * 2 output voltage 1 output voltage 2 output voltage 3 output voltage 4 output voltage 5 output voltage 6 output voltage 7 v dd 2 v dd 3 v dd 4 v dd 1, v dd 5, v dd 6, v dd 7 rst, dsgat, ssi, ssk, sen, fri, hri ebcksm test rg h1, h2 xshp, xshd, xrs, pblk, xclpdm 3/2mck, mck, cld 1/2mck xv1, xv2, xv3, xsub, xsg1, xsg2, xclpob, id, wen fro, hro v dd a v dd b v dd c v dd d v ih1 v il1 v ih2 v il2 v ih3 v il3 v oh1 v ol1 v oh2 v ol2 v oh3 v ol3 v oh4 v ol4 v oh5 v ol5 v oh6 v ol6 v oh7 v ol7 3.0 3.0 3.0 3.0 0.8v dd d 0.8v dd d 0.7v dd d v dd a ?0.8 v dd b ?0.8 v dd c ?0.8 v dd d ?0.8 v dd d ?0.8 v dd d ?0.8 v dd d ?0.8 3.3 3.3 3.3 3.3 3.6 3.6 3.6 3.6 0.2v dd d 0.2v dd d 0.3v dd d 0.4 0.4 0.4 0.4 0.4 0.4 0.4 v v v v v v v v v v v v v v v v v v v v v v v v feed current where i oh = ?.3ma pull-in current where i ol = 2.4ma feed current where i oh = ?0.4ma pull-in current where i ol = 7.2ma feed current where i oh = ?.3ma pull-in current where i ol = 2.4ma feed current where i oh = ?0.4ma pull-in current where i ol = 7.2ma feed current where i oh = ?.3ma pull-in current where i ol = 2.4ma feed current where i oh = ?.4ma pull-in current where i ol = 4.8ma feed current where i oh = ?.6ma pull-in current where i ol = 7.2ma
? 6 CXD2452R inverter i/o characteristics for oscillation (within the recommended operating conditions) logical vth input voltage output voltage feedback resistor oscillation frequency osci osci osco osci, osco osci, osco lvth v ih v il v oh v ol rfb f 0.7v dd d v dd d/2 500k 20 v dd d/2 2m 0.3v dd d v dd d/2 5m 50 v v v v v mhz feed current where i oh = ?.0ma pull-in current where i ol = 6.0ma v in = v dd d or vss inverter input characteristics for base oscillation clock duty adjustment (within the recommended operating conditions) logical vth input voltage input amplitude 3mck lvth v ih v il v in 0.7v dd d 0.3 v dd d/2 0.3v dd d v v v vp-p fmax 50mhz sine wave * 1 input voltage is the input voltage characteristics for direct input from an external source. input amplitude is the input amplitude characteristics in the case of input through capacitor. item pins symbol conditions min. typ. max. unit item pins symbol conditions min. typ. max. unit
? 7 CXD2452R ac characteristics 1) ac characteristics between the serial interface clocks 0 . 8 v d d d 0 . 8 v d d d 0 . 2 v d d d 0 . 2 v d d d 0 . 2 v d d d 0 . 8 v d d d t h 1 t s 1 t h 2 t s 2 t s 3 s s i s s k s e n s e n (within the recommended operating conditions) symbol t s1 t h1 t s2 t h2 t s3 ssi setup time, activated by the rising edge of ssk ssi hold time, activated by the rising edge of ssk ssk setup time, activated by the rising edge of sen ssk hold time, activated by the rising edge of sen sen setup time, activated by the rising edge of ssk 20 20 20 20 20 ns ns ns ns ns definition min. typ. max. unit 2) serial interface clock internal loading characteristics 0 . 2 v d d d 0 . 8 v d d d t h 4 t s 4 h r i x s g 1 s e n 0 . 2 v d d d f r i h r i x s g 1 e n l a r g e d v i e w e x a m p l e : d u r i n g r e c o r d i n g d r i v e m o d e note) be sure to maintain a constantly high sen logic level near the hri fall immediately before xsg1 generation. symbol t s4 t h4 sen setup time, activated by the falling edge of hri sen hold time, activated by the falling edge of hri 0 0 ns ns definition min. typ. max. unit (within the recommended operating conditions)
? 8 CXD2452R (within the recommended operating conditions) symbol t pdpulse output signal delay, activated by the rising edge of sen 5 100 ns definition min. typ. max. unit 5) phase identification characteristics using fri and hri input 0 . 2 v d d d f r i h r i t p d 1 t h e f i e l d i s i d e n t i f i e d a s a n o d d f i e l d . 0 . 2 v d d d f r i h r i t p d 1 t h e f i e l d i s i d e n t i f i e d a s a n e v e n f i e l d . w h e n t h e h r i l o g i c l e v e l i s l o w t p d 1 a f t e r t h e f a l l i n g e d g e o f f r i w h e n t h e h r i l o g i c l e v e l i s h i g h t p d 1 a f t e r t h e f a l l i n g e d g e o f f r i (within the recommended operating conditions) symbol t pd1 field identification clock phase, activated by the falling edge of fri 1100 1300 ns definition min. typ. max. unit 4) rst loading characteristics 0 . 8 v d d d t w 1 0 . 2 v d d d r s t (within the recommended operating conditions) symbol t w1 rst pulse width 35 ns definition min. typ. max. unit 3) serial interface clock output variation characteristics normally, the serial interface data is loaded to the CXD2452R at the timing shown in 2) above. however, one exception to this is when the data such as ssgsel and stb is loaded to the CXD2452R and controlled at the rising edge of sen. for stb, see control data d62 to d63 stb in ?escription of operation? 0 . 8 v d d d t p d p u l s e s e n o u t p u t s i g n a l
? 9 CXD2452R 7) output timing characteristics using dsgat t p d s g a t 0 . 2 v d d d 0 . 2 v d d d d s g a t h 1 , h 2 , r g , x v 1 , x v 2 , x v 3 , x s u b , x s g 1 , x s g 2 , x s h p , x s h d , x r s , p b l k , x c l p d m , x c l p o b , c l d h1 and h2 load capacitance = 100pf, rg load capacitance = 20pf, xv1, xv2, xv3, xsg1, xsg2, xsub, xshp, xshd, xrs, pblk, xclpdm, xclpob and cld load capacitance = 10pf (within the recommended operating conditions) symbol t pdsgat time until the above outputs go low after the fall of dsgat 100 ns definition min. typ. max. unit 6) fri and hri loading characteristics f r i , h r i m c k 0 . 8 v d d d t h 5 t s 5 0 . 8 v d d d 0 . 8 v d d d mck load capacitance = 10pf (within the recommended operating conditions) symbol t s5 t h5 fri and hri setup time, activated by the rising edge of mck fri and hri hold time, activated by the rising edge of mck 10 0 ns ns definition miin. typ. min. unit 8) output variation characteristics m c k w e n , i d 0 . 8 v d d d t p d 2 symbol t pd2 time until the above outputs change after the rise of mck 20 40 ns definition miin. typ. min. unit wen and id load capacitance = 10pf (within the recommended operating conditions)
? 10 CXD2452R 9) h1 and rg waveform characteristics 0 . 9 v d d b 0 . 1 v d d b 0 . 9 v d d b 0 . 1 v d d b t f h 1 t r h 1 0 . 9 v d d a 0 . 1 v d d a t r r g 0 . 9 v d d a 0 . 1 v d d a t f r g r g h 1 v dd b = 3.3v, topr = 25 c, h1 and h2 load capacitance = 100pf, rg load capacitance = 20pf (within the recommended operating conditions) symbol t rh1 t fh1 t rrg t frg h1 rise time h1 fall time rg rise time rg fall time 10 10 3 3 ns ns ns ns definition min. typ. max. unit 10) i/o pin capacitance symbol c in c out c i/o input pin capacitance output pin capacitance i/o pin capacitance 9 11 11 pf pf pf definition min. typ. max. unit (within the recommended operating conditions)
? 11 CXD2452R the CXD2452R basically loads and reflects the serial interface data sent in the above format in the readout portion at the falling edge of hri. here, readout portion specifies the horizontal interval during which xsg1 rises. there are two types of serial interface data: drive control data and phase adjustment data. hereafter, these data are distinguished by referring to the former as control data and the latter as adjustment data. an example of the initialization data for the CXD2452R control data is shown below. this data is based on the application circuit block diagram, so care should be taken as there are some differences from the rst pin initialization data. concretely, the internal ssg operates, the xclpob and id pulses are generated, and the 3/2 mck pulse is stopped. this data shows the values when the ebcksm pin is low and d64 to d71 chksum is valid. description of operation all pulses output from the CXD2452R are controlled by the rst and dsgat pins and by the serial interface data shown below. the details of control by the serial interface data and a description of operation are as follows. 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 s s i s s k s e n msb lsb d71 d70 d69 d68 d67 d66 d65 d64 d63 d62 d61 d60 d59 d58 d57 d56 msb lsb d55 d54 d53 d52 d51 d50 d49 d48 d47 d46 d45 d44 d43 d42 d41 d40 msb lsb d39 d38 d37 d36 d35 d34 d33 d32 d31 d30 d29 d28 d27 d26 d25 d24 msb lsb d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d09 d08 msb lsb d07 d06 d05 d04 d03 d02 d01 d00 1 0 1 0 1 1 0 1 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 the adjustment data does not normally need to be set. however, when adjustment is difficult due to the system configuration or for other reasons, the data considered most appropriate at that time should be set as the initialization data.
? 12 CXD2452R data d00 to d07 d08 to d15 d16 to d17 d18 to d25 d26 to d35 d36 to d47 d48 d49 to d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 d60 to d61 d62 to d63 d64 to d71 chip ctgry smd shut.frm shut.hd expose psmt ssgsel wensel clpsel idsel hmcksel tmcksel hmckrev tmckrev dsg stb chksum chip switching category switching electronic shutter mode setting electronic shutter vertical interval setting electronic shutter horizontal interval setting recording exposure setting switching drive mode switching internal ssg operation switching wen pulse operation switching xclpob pulse operation switching id pulse operation switching 1/2mck pulse operation switching 3/2mck pulse operation switching 1/2mck pulse reset polarity switching 2/3mck pulse reset polarity switching pulse generation control ic pin status control check sum bit see d00 to d07 chip. see d08 to d15 ctgry. see d16 to d35 electronic shutter mode. see d16 to d35 electronic shutter mode. see d16 to d35 electronic shutter mode. all 0 all 0 all 0 all 0 all 0 all 0 0 all 0 0 0 0 0 0 0 0 0 0 all 0 all 0 all 0 symbol function data = 0 data = 1 when a reset off monitoring off on off off off on positive polarity negative polarity on recording on off on on on off negative polarity positive polarity see d60 to d61 dsg table. see d62 to d63 stb table. see d64 to d71 chksum. control data
? 13 CXD2452R detailed description of each data d00 to d07 chip the serial interface data is loaded to the CXD2452R when d00 and d07 are 1. however, this assumes that either the ebcksm pin is low and d64 to d71 chksum is satisfied or the ebcksm pin is high. d08 to d15 ctgry of the data provided to the CXD2452R by the serial interface, the CXD2452R loads d16 and subsequent data to the control register side when d08 is 0, and to the adjustment register side when d08 is 1. however, this assumes that the CXD2452R is selected by chip and that either the ebcksm pin is low and d64 to d71 chksum is satisfied or the ebcksm pin is high. msb lsb d07 d06 d05 d04 d03 d02 d01 d00 1 0 0 0 0 0 0 1 function loading to the CXD2452R msb lsb d15 d14 d13 d12 d11 d10 d09 d08 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 function loading to the control register side loading to the adjustment register side d16 to d35 electronic shutter mode the CXD2452R's electronic shutter mode can be switched as follows by smd d16 to d17 . handling of the data from d18 to d35 differs according to the mode, and is explained in detail below. d17 d16 description of operation xsub stopped mode high-speed/low-speed shutter mode htsg control mode 0 1 1 x 0 1 the electronic shutter data is expressed as shown in the table below using shut.hd as an example. msb lsb d35 d34 d33 d32 d31 d30 d29 d28 d27 d26 0 1 1 1 0 0 0 0 1 1 1 c 3 [xsub stopped mode] during this mode, the data from d18 to d35 is invalid. the shutter speed is 1/60s during monitoring drive mode, and 1/30s during recording drive mode. shut.hd is expressed as 1c3h . note that when sen is shared with other ics and indentification is performed using chip-id, the CXD2452R data must be positioned immeditately before the load timing, that is to say at the very end. note that the CXD2452R cannot apply both categories simultaneously during the same vertical interval. also, care should be taken as the data is overwritten even if the same category is applied.
? 14 CXD2452R the CXD2452R does not distinguish between the high-speed shutter and low-speed shutter modes. the interval during which shut.frm and shut.hd are specified together is the shutter speed. at this time, shut.frm controls the xsg1, xsg2 output, and shut.hd controls the xsub output. concretely, when specifying high-speed shutter, shut.frm is set to 00h. (see the figure.) during low-speed shutter, or in other words when shut.frm is set to 01h or higher, the serial interface data is not loaded until this interval is finished. however, care should be taken as the vertical interval indicated here is set in 1/60s units when the drive mode is monitoring drive mode and 1/30s units during recording drive mode. for monitoring drive mode, care should be taken that shut.hd value is offset. this is because the same exposure time can be obtained for the same shut.hd data without depending on drive mode basically for high- speed shutter. formula for calculating the electronic shutter speed: [shut.frm/shut.hd] (unit: s) monitoring drive mode: t = shut.frm * 1.66834 * 10 4 + {(20ch ?shut.hd) * 780 + 447} * 81.5 * 10 ? (107h shut.hd 20ch) s h u t . f r m 0 1 0 1 0 1 s h u t . h d - 1 0 6 h 0 0 h 0 1 h 0 0 h 1 a 6 h a a 1 d d h 1 a 6 h s h u t . h d w e n s m d s h u t . f r m x s u b f r i x s g 1 during monitoring drive mode/low-speed shutter mode s h u t . f r m 0 1 s h u t . h d 0 1 h 0 1 0 0 h 1 a 6 h a a 1 d d h s h u t . h d w e n s m d s h u t . f r m x s u b f r i x s g 1 during recording drive mode/low-speed shutter mode recording drive mode: t = shut.frm * 3.33667 * 10 4 + {(20ch ?shut.hd) * 780 + 447} * 81.5 * 10 ? (000h shut.hd 20ch) [high-speed/low-speed shutter mode] during this mode, the data has the following meanings. symbol data description shutter speed data (number of vertical intervals) specification shutter speed data (number of horizontal intervals) specification d18 to d25 d26 to d35 shut.frm shut.hd
? 15 CXD2452R shut.frm 00h 00h 00h 00h 00h 00h 00h 00h 00h 20ch 20bh 209h 205h 1fdh 1edh 1ceh 18fh 16fh 1/27000 1/10000 1/4500 1/2000 1/1000 1/500 1/250 1/125 1/100 1/27450 1/10000 1/4403 1/2077 1/1010 1/498 1/251 1/125 1/100 00h 01h 01h 02h 07h 09h 00h 00h 00h 107h * 1 20ch 1d8h 20ch 18bh 109h 0d2h 083h 000h 1/60 1/60 * 2 1/50 * 2 1/30 * 2 1/8 * 2 1/6 * 2 1/50 * 3 1/40 * 3 1/30 * 3 1/60 1/60 1/50 1/30 1/8 1/6 1/50 1/40 1/30 shut.hd calculation results (s) shutter speed (s) shut.frm calculation results (s) shutter speed (s) shut.hd electronic shutter speed table [shut.frm/shut.hd] * 1 one xsub pulse is generated for odd fields and two for even fields. * 2 these are the settings during monitoring drive mode. * 3 these can only be specified during recording drive mode. note) input prohibited data: monitoring drive mode 000h to 106h recording drive mode and monitoring drive mode 20dh to 3ffh [htsg control mode] during this mode, the data from d18 to d35 is invalid. the shutter speed is the value obtained by adding the shutter speed specified in the preceding vertical interval to the vertical period during which xsg1 (and xsg2) is stopped as shown in the figure. x s u b f r i x s g 1 w e n 0 1 1 1 0 1 s m d v c k during htsg control mode
? 16 CXD2452R d51 psmt 0: driving is controlled in accordance with monitoring drive mode under the assumption that vertical/horizontal sync signals are input. 1: driving is controlled in accordance with recording drive mode under the assumption that vertical/horizontal sync signals are input. see the timing charts for the vertical/horizontal sync signals in accordance with each mode. note that when switching from monitoring drive to recording drive mode, the pixels decimated thus far must be cleaned. concretely, this operation is supported by generating xsub, but the CXD2452R facilitates this control by using d48 expose. (see the figure.) f r i x s g 1 w e n 0 0 0 0 s m d x s u b 0 0 0 0 0 0 e x p o s e 1 0 1 0 p s m t 0 0 r e c o r d i n g m o n i t o r i n g m o n i t o r i n g e x p o s u r e t i m e m o d e m o n i t o r i n g image of switching from monitoring drive mode to recording drive mode d52 ssgsel 0: internal ssg functions are stopped. 1: internal ssg functions operate, and fro and hro are generated. when generation is stopped, these pulses are fixed low. d53 wensel 0: wen is generated. 1: wen generation is stopped. when generation is stopped, operation is the same as for d52 ssgsel. d48 expose 0: no operation 1: xsub for recording exposure is generated. this control specification is such that one xsub pulse is always generated during the horizontal interval immediately following the readout portion even if the electronic shutter speed is set to 1/60s (smd = 00). this mode is closely related to d51 psmt, so see d51 regarding the control.
? 17 CXD2452R no control performed ccd pulse control sample-and-hold and analog/digital conversion ic pulse control ccd pulse and sample-and-hold and analog/digital conversion ic pulse control d60 to d61 dsg the CXD2452R can stop control to the ccd pulses and pulses for the sample-and-hold and analog/digital conversion ics by setting the dsgat pin low. conversely, when the dsgat pin is set high, the controlled pulses can be switched as follows using the serial interface data. d61 d60 operating mode 0 1 0 1 0 0 1 1 here, ccd pulses refer to the h1, h2, rg, xv1, xv2, xv3, xsub, xsg1 and xsg2 pulses. sample-and-hold and analog/digital conversion ic pulses refer to the xshp, xshd, xrs, pblk, xclpob, xclpdm and cld pulses. see 7) output timing characteristics using dsgat of "ac characteristics" for the stop control status of each pulse. d54 clpsel 0: xcpob generation is stopped. 1: xcpob is generated. when generation is stopped, operation is the same as for d52 ssgsel. d55 idsel 0: id generation is stopped. 1: id is generated. when generation is stopped, operation is the same as for d52 ssgsel. d56 hmcksel 0: 1/2mck generation is stopped. 1: 1/2mck is generated. when generation is stopped, operation is the same as for d52 ssgsel. d57 tmcksel 0: 3/2mck is generated. 1: 3/2mck generation is stopped. when generation is stopped, operation is the same as for d52 ssgsel. d58 hmckrev 0: 1/2mck reset when positive polarity. 1: 1/2mck reset when negative polarity. d59 hmckrev 0: 3/2mck reset when negative polarity. 1: 3/2mck reset when positive polarity.
? 18 CXD2452R d62 to d63 stb this switches the operating mode as shown below. however, the ic pin status control bit is loaded to the CXD2452R and controlled immediately at the rise of the sen input. normal operation mode sleep mode * 1 standby mode d63 d62 symbol 0 1 1 x 0 1 camera sleep stnby operating mode * 1 mode for the status which does not require ccd drive when playing back recorded data within the system. the pin status during each mode is shown in the table below. pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 3mck vss1 wen id test v dd 1 xclpob v dd 2 rg vss2 vss3 h1 h2 v dd 3 xclpdm v dd 4 xshp xshd xrs vss4 pblk 1/2mck 3/2mck v dd 5 act act act act act act act act act act act act act act act l l l l l l l l l l l l act act l l l l l l l l l l l l l symbol camera sleep stnby note) act means that the circuit is operating. l indicates a low output level in the controlled status. pin symbol camera sleep stnby 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 rst v dd 6 ssi ssk sen ebcksm fro hro hri fri cld v ss 5 dsgat mck vss6 xsub xv3 xsg2 xsg1 xv2 v dd 7 xv1 osco osci act act act act act act act act act act act act act act act act act act act act act act act act act act act act act l act act l l l l l l act act act act act act act l l act act l act l l l l l l l act act
? 19 CXD2452R d64 to d71 chksum this is the check sum bit. apply the data shown below. msb lsb d07 d06 d05 d04 d03 d02 d01 d00 d15 d14 d13 d12 d11 d10 d09 d08 d23 d22 d21 d20 d19 d18 d17 d16 d31 d30 d29 d28 d27 d26 d25 d24 d39 d38 d37 d36 d35 d34 d33 d32 d47 d46 d45 d44 d43 d42 d41 d40 d55 d54 d53 d52 d51 d50 d49 d48 d63 d62 d61 d60 d59 d58 d57 d56 +) d71 d70 d69 d68 d67 d66 d65 d64 ? chksum 0 0 0 0 0 0 0 0 ? reflected when the total is 0.
? 20 CXD2452R f r i h r i x s g 1 x s g 2 x s u b x v 1 x v 2 x v 3 c c d o u t 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 4 9 0 4 9 1 4 9 2 4 9 3 4 9 4 1 2 1 2 3 4 5 6 7 8 1 p b l k x c l p o b x c l p d m w e n i d * t h e n u m b e r o f x s u b p u l s e s i s d e t e r m i n e d b y t h e s e r i a l i n t e r f a c e d a t a . t h i s c h a r t s h o w s t h e c a s e w h e r e s h u t . h d = 2 0 c h a n d x s u b p u l s e s a r e g e n e r a t e d o v e r t h e e n t i r e h o r i z o n t a l i n t e r v a l . * i n a d d i t i o n t o t h e p h a s e r e l a t i o n s h i p b e t w e e n f r i a n d h r i s h o w n a b o v e , t h e p h a s e s m a y a l s o b e o f f s e t b y 1 / 2 h o r i z o n t a l i n t e r v a l . i n a n y c a s e , t h e r e a d o u t i n t e r v a l i s t h e 9 t h h r i f a l l c o u n t e d f r o m t h e f a l l o f f r i . * n o t e t h a t r a n d b o f c c d o u t i n d i c a t e l i n e s c o n t a i n i n g t h e s e c o m p o n e n t s , a n d d o n o t m e a n t h e l e a d p i x e l c o m p o n e n t o f t h a t l i n e . 5 2 5 1 5 2 5 1 r r r r b b b b r r b b b r chart-1 vertical direction timing chart mode (base oscillation frequency: 2340f h ) recording drive mode applicable ccd image sensor icx098ak
? 21 CXD2452R f r i h r i x s g 1 x s g 2 x s u b x v 1 x v 2 x v 3 c c d o u t 1 2 5 6 1 2 5 6 9 1 0 1 3 1 4 1 7 1 8 2 1 2 2 2 5 2 6 2 9 4 6 6 4 6 9 4 7 0 4 7 3 4 7 4 1 2 5 6 1 2 5 6 9 1 0 1 3 1 4 p b l k x c l p o b x c l p d m w e n i d * t h e n u m b e r o f x s u b p u l s e s i s d e t e r m i n e d b y t h e s e r i a l i n t e r f a c e d a t a . t h i s c h a r t s h o w s t h e c a s e w h e r e s h u t . h d = 2 0 c h a n d x s u b p u l s e s a r e g e n e r a t e d o v e r t h e e n t i r e h o r i z o n t a l i n t e r v a l . * n o t e t h a t r a n d b o f c c d o u t i n d i c a t e l i n e s c o n t a i n i n g t h e s e c o m p o n e n t , a n d d o n o t m e a n t h e l e a d p i x e l c o m p o n e n t o f t h a t l i n e . 5 2 5 1 2 6 2 4 8 2 4 8 5 4 8 6 4 8 9 4 9 0 4 9 3 4 9 4 4 8 1 4 8 2 4 8 5 4 8 6 4 8 9 4 7 7 4 7 8 4 9 4 4 9 0 4 9 3 b b b b r r r r r r r r r r r b b b b b b b r b r r r b b b b b b b b b b b r r r r r r r chart-2 vertical direction timing chart mode (base oscillation frequency: 2340f h ) monitoring drive mode applicable ccd image sensor icx098ak
? 22 CXD2452R * t h e h r i o f t h i s c h a r t i s e q u i v a l e n t t o h r i ' o f c h a r t - 7 . t h i s h r i i n d i c a t e s a t i m i n g t h a t t h e c x d 2 4 5 2 r t a k e s i n a c t u a l l y . * t h e n u m b e r s a t t h e o u t p u t p u l s e t r a n s i t i o n p o i n t s i n d i c a t e t h e c o u n t a t t h e m c k ( 7 8 0 f h ) r i s e f r o m t h e f a l l o f h r i . * t h e h r i f a l l i n t e r v a l s h o u l d b e b e t w e e n 3 . 6 t o 9 . 4 s . t h i s c h a r t s h o w s a n i n t e r v a l o f 7 8 c k ( 6 . 3 s ) . * x s u b i s o u t p u t a t t h e t i m i n g s h o w n a b o v e w h e n s p e c i f i e d b y t h e s e r i a l i n t e r f a c e d a t a . * t h e i d t r a n s i t i o n t i m i n g i s s y n c h r o n i z e d w i t h t h e f a l l o f x v 3 . * w e n i s o u t p u t d u r i n g t h e h o r i z o n t a l i n t e r v a l s h o w n i n c h a r t - 1 . t h e t r a n s i t i o n t i m i n g i s t h e s a m e a s t h a t f o r i d . * r , g a n d b o f h 1 i n d i c a t e t h e o u t p u t p i x e l c o l o r . i n a d d i t i o n t o t h e l i n e s s t a r t i n g f r o m r a n d g s h o w n a b o v e , t h e r e a r e a l s o l i n e s s t a r t i n g f r o m g a n d b . 0 5 0 1 0 0 5 5 0 h r i m c k h 1 x v 1 x v 2 x v 3 x s g 1 x s g 2 x s u b r g p b l k x c l p o b x c l p d m i d w e n 4 4 8 0 5 6 9 2 6 8 1 0 4 1 0 4 8 1 1 2 9 1 2 9 1 1 8 4 4 2 1 4 0 6 8 6 8 4 3 1 1 6 g g g g g b b b b b b b b b g g g g g g r g r r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r r chart-3 horizontal direction timing chart mode (base oscillation frequency: 2340f h ) recording drive mode applicable ccd image sensor icx098ak
? 23 CXD2452R 0 5 0 1 0 0 5 5 0 h r i m c k h 1 x v 1 x v 2 x v 3 x s g 1 x s g 2 x s u b r g p b l k x c l p o b x c l p d m i d w e n 4 4 8 0 5 6 9 2 6 8 1 0 4 1 0 4 8 1 1 2 9 1 1 8 2 1 4 0 6 8 6 8 4 3 1 1 6 * t h e h r i o f t h i s c h a r t i s e q u i v a l e n t t o h r i ' o f c h a r t - 7 . t h i s h r i i n d i c a t e s a t i m i n g t h a t t h e c x d 2 4 5 2 r t a k e s i n a c t u a l l y . * t h e n u m b e r s a t t h e o u t p u t p u l s e t r a n s i t i o n p o i n t s i n d i c a t e t h e c o u n t a t t h e m c k ( 7 8 0 f h ) r i s e f r o m t h e f a l l o f h r i . * t h e h r i f a l l i n t e r v a l s h o u l d b e b e t w e e n 3 . 6 t o 9 . 4 s . t h i s c h a r t s h o w s a n i n t e r v a l o f 7 8 c k ( 6 . 3 s ) . * x s u b i s o u t p u t a t t h e t i m i n g s h o w n a b o v e w h e n s p e c i f i e d b y t h e s e r i a l i n t e r f a c e d a t a . * t h e i d t r a n s i t i o n t i m i n g i s s y n c h r o n i z e d w i t h t h e f a l l o f x v 3 . i d i s r e s e t l o w a t t h i s t i m i n g d u r i n g t h e r e a d o u t h o r i z o n t a l i n t e r v a l . * w e n i s o u t p u t d u r i n g t h e h o r i z o n t a l i n t e r v a l s h o w n i n c h a r t - 1 . t h e t r a n s i t i o n t i m i n g i s t h e s a m e a s t h a t f o r i d . 1 1 6 5 2 1 5 2 0 5 5 1 5 2 0 5 5 1 chart-4 horizontal direction timing chart mode (base oscillation frequency: 2340f h ) recording drive mode (readout portion) applicable ccd image sensor icx098ak
? 24 CXD2452R * t h e h r i o f t h i s c h a r t i s e q u i v a l e n t t o h r i ' o f c h a r t - 7 . t h i s h r i i n d i c a t e s a t i m i n g t h a t t h e c x d 2 4 5 2 r t a k e s i n a c t u a l l y . * t h e n u m b e r s a t t h e o u t p u t p u l s e t r a n s i t i o n p o i n t s i n d i c a t e t h e c o u n t a t t h e m c k ( 7 8 0 f h ) r i s e f r o m t h e f a l l o f h r i . * t h e h r i f a l l i n t e r v a l s h o u l d b e b e t w e e n 3 . 6 t o 9 . 4 s . t h i s c h a r t s h o w s a n i n t e r v a l o f 7 8 c k ( 6 . 3 s ) . * x s u b i s o u t p u t a t t h e t i m i n g s h o w n a b o v e w h e n s p e c i f i e d b y t h e s e r i a l i n t e r f a c e d a t a . * t h e i d t r a n s i t i o n t i m i n g i s s y n c h r o n i z e d w i t h t h e f a l l o f x v 3 . * w e n i s o u t p u t d u r i n g t h e h o r i z o n t a l i n t e r v a l s h o w n i n c h a r t - 2 . t h e t r a n s i t i o n t i m i n g i s t h e s a m e a s t h a t f o r i d . * r , g a n d b o f h 1 i n d i c a t e t h e o u t p u t p i x e l c o l o r . i n a d d i t i o n t o t h e l i n e s s t a r t i n g f r o m r a n d g s h o w n a b o v e , t h e r e a r e a l s o l i n e s s t a r t i n g f r o m g a n d b . x v 1 x v 2 x v 3 x s g 1 x s g 2 x s u b r g p b l k x c l p o b x c l p d m i d w e n 4 4 8 0 5 0 6 8 5 8 1 1 0 1 0 4 8 1 1 2 9 1 2 9 1 1 8 4 4 2 1 4 0 9 2 9 2 6 2 9 8 8 6 1 0 4 7 4 9 2 0 5 0 1 0 0 5 5 0 h r i m c k h 1 4 3 1 1 6 g g g g g b b b b b b b b b g g g g g g r g r r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r r chart-5 horizontal direction timing chart mode (base oscillation frequency: 2340f h ) monitoring drive mode applicable ccd image sensor icx098ak
? 25 CXD2452R 0 5 0 1 0 0 5 5 0 h r i m c k h 1 x v 1 x v 2 x v 3 x s g 1 x s g 2 x s u b r g p b l k x c l p o b x c l p d m i d w e n 4 4 8 0 5 0 6 8 5 8 1 1 0 1 0 4 8 1 1 2 9 1 1 8 2 1 4 0 9 2 9 2 4 3 1 1 6 * t h e h r i o f t h i s c h a r t i s e q u i v a l e n t t o h r i ' o f c h a r t - 7 . t h i s h r i i n d i c a t e s a t i m i n g t h a t t h e c x d 2 4 5 2 r t a k e s i n a c t u a l l y . * t h e n u m b e r s a t t h e o u t p u t p u l s e t r a n s i t i o n p o i n t s i n d i c a t e t h e c o u n t a t t h e m c k ( 7 8 0 f h ) r i s e f r o m t h e f a l l o f h r i . * t h e h r i f a l l i n t e r v a l s h o u l d b e b e t w e e n 3 . 6 t o 9 . 4 s . t h i s c h a r t s h o w s a n i n t e r v a l o f 7 8 c k ( 6 . 3 s ) . * x s u b i s o u t p u t a t t h e t i m i n g s h o w n a b o v e w h e n s p e c i f i e d b y t h e s e r i a l i n t e r f a c e d a t a . * t h e i d t r a n s i t i o n t i m i n g i s s y n c h r o n i z e d w i t h t h e f a l l o f x v 3 . i d i s r e s e t l o w a t t h i s t i m i n g d u r i n g t h e r e a d o u t h o r i z o n t a l i n t e r v a l . * w e n i s o u t p u t d u r i n g t h e h o r i z o n t a l i n t e r v a l s h o w n i n c h a r t - 2 . t h e t r a n s i t i o n t i m i n g i s t h e s a m e a s t h a t f o r i d . 6 2 9 8 8 6 1 0 4 7 4 9 2 1 1 6 5 2 1 5 5 1 5 2 0 chart-6 horizontal direction timing chart mode (base oscillation frequency: 2340f h ) monitoring drive mode (readout portion) applicable ccd image sensor icx098ak
? 26 CXD2452R h r i h r i ' * t h e p h a s e r e l a t i o n s h i p o f e a c h p u l s e i n d i c a t e s l o g i c a l p o s i t i o n . f o r a c t u a l o u t p u t w a v e f o r m , d e l a y i s a d d e d r e s p e c t i v e l y . * h r i ' i n d i c a t e s t h e h r i , w h i c h i s a t i m i n g t h a t t a k e n i n a c t u a l l y . * 3 / 2 m c k a n d 1 / 2 m c k c a n i n v e r s e p o l a r i t y a c c o r d i n g t o e a c h s e r i a l i n t e r f a c e d a t a . t h i s c h a r t i n d i c a t e s t h a t 3 / 2 m c k i s n e g a t i v e p o l a r i t y ; 1 / 2 m c k i s p o s i t i v e p o l a r i t y . 3 m c k 3 / 2 m c k 1 / 2 m c k c l d m c k h 1 h 2 r g x s h p x s h d x r s 4 3 1 1 6 1 1 4 3 1 1 6 chart-7 high-speed phase timing chart mode (base oscillation frequency: 2340f h ) applicable ccd image sensor icx098ak
? 27 CXD2452R application circuit block diagram 5 1 7 1 8 1 9 2 1 1 5 3 5 2 3 2 2 4 3 3 8 3 4 3 3 3 2 3 1 2 9 2 8 2 7 3 0 3 7 2 5 4 8 4 7 1 4 6 4 4 4 1 4 3 4 2 4 0 c l d i d 1 / 2 m c k w e n m c k f r i h r i h r o f r o x s h p x c l p o b x c l p d m p b l k x r s x s h d v - d r c x d 1 2 6 7 a n x v 1 x v 3 x s g 1 x s g 2 x s u b v s u b v 3 v 2 b v 2 a v 1 1 2 1 3 9 h 1 h 2 r g c c d i c x 0 9 8 a k c c d o u t d r v o u t v r t v r b a / d c x d 2 3 1 1 a r d 0 t o 9 1 0 t g c x d 2 4 5 2 r s s g e b c k s m t e s t d s g a t r s t o s c i o s c o 3 m c k c o n t r o l l e r s e n s s k s s i x v 2 7 3 / 2 m c k s / h c x a 2 0 0 6 q s i g n a l p r o c e s s i n g b l o c k application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same . note) when the cxd2311ar is used as a/d converter, cld must be inversed.
? 28 CXD2452R package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n p l a t i n g 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e 4 8 p i n l q f p ( p l a s t i c ) 9 . 0 0 . 2 * 7 . 0 0 . 1 1 1 2 1 3 2 4 2 5 3 6 3 7 4 8 ( 0 . 2 2 ) 0 . 1 8 0 . 0 3 + 0 . 0 8 0 . 2 g l q f p - 4 8 p - l 0 1 l q f p 0 4 8 - p - 0 7 0 7 ( 8 . 0 ) 0 . 5 0 . 2 0 . 1 2 7 0 . 0 2 + 0 . 0 5 a 1 . 5 0 . 1 + 0 . 2 0 . 1 s o l d e r / p a l l a d i u m n o t e : d i m e n s i o n * d o e s n o t i n c l u d e m o l d p r o t r u s i o n . 0 . 1 0 . 1 0 . 5 0 . 2 0 t o 1 0 d e t a i l a 0 . 1 3 m 0 . 5 s s b d e t a i l b : s o l d e r ( 0 . 1 8 ) ( 0 . 1 2 7 ) d e t a i l b : p a l l a d i u m 0 . 1 2 7 0 . 0 4 0 . 1 8 0 . 0 3 + 0 . 0 8 0 . 1 2 7 0 . 0 2 + 0 . 0 5 0 . 1 8 0 . 0 3

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